1. Field of the Invention
The present invention relates to a method for manufacturing a dynamic random access memory (DRAM) array, and more particularly to a method of generating a photomask layout for DRAM devices with cylindrical capacitor arrays.
2. Description of the Prior Art
A DRAM cell comprises metal-oxide-semiconductor field effect transistors (MOSFETs) and capacitors that are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of DRAM. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become continuously decreasing so that the packing densities of these DRAM devices have increased considerably. These high density DRAMs offer the advantages of longer refresh time as well as less power consumption. However, as the sizes of the capacitors become smaller, so as the capacitance of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing the performance problem. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
There are two ways to deal with this problem: decreasing the thickness of the capacitor dielectric layer (ONO) or increasing the surface area of the capacitors. Since decreasing the thickness of the capacitor dielectric layer (ONO) almost reaches its physical limitation already, increasing the capacitor surface area becomes an easier approach when the capacitor is used to fabricate 64 Mbit DRAMs and beyond. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. of Hyundai Electronics (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. of Fujisu (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. U.S. Pat. No. 5,021,357 to Choi et al. of Samsung (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cylinder-shaped capacitor structure.
Referring now more particularly to FIG. 1, there is shown a typical cross-sectional view of a DRAM cell comprising of the cylindrical capacitor array. First, a P-well and an N-well (not shown in the Figure) are formed in a silicon substrate 100. Next, shallow trench isolation (STI) (not shown in the Figure) is sequentially formed by the techniques well known in the art. Wordlines 20 including gate dielectric 21, polysilicon gate electrode 22, lightly doped drains (LDDs) (not shown in the Figure), source/drain (S/D) regions 23 and sidewall spacers 24 are then formed upon the semiconductor silicon substrate. Next, an inter-polysilicon oxide (IPO) layer 30 is deposited and planarized by chemical mechanical polishing (CMP). Thereafter, first polysilicon plugs 40 are formed followed by sequentially depositing an etch stop layer 50 and an oxide layer 60 over the IPO layer 30. The etch stop layer 50 is typically composed of silicon nitride or oxynitride.
Next, storage nodes 80 together with the protection trenches are formed by the conventional photolithography and anisotropic etching techniques. The storage nodes are typically made of hemispherical grained silicon (HSG-Si) which is grown on the surface of a thin polysilicon base layer over the oxide layer 60. Thereafter, excess HSG-Si 80 and polysilicon seed layer are removed by CMP to obtain electrically isolated crown capacitors. Finally, capacitor dielectric layer (not shown in the Figure for simplicity reason) and top plate 90 of the capacitors are sequentially deposited upon the cylindrical capacitors. The capacitor dielectric layer is typically using high dielectric constant composite oxide/nitride layers such as ONO or NO to obtain enough capacitance pre unit cell for high density DRAM applications.
Referring now to FIG. 2, there is shown a conventional photomask layout used for defining cylindrical capacitors 70. There is a protection trench 100 around capacitor arrays that can protect capacitor arrays from being damaged by solvent or acids in the subsequent violent processes. The typical shape of the protection trench is a scribed line like rectangular strips.
However, the sizes of both the DRAM cell and the capacitors are continuously decreasing when entering sub-micron or even deep sub-micron technology era. The process window becomes smaller that requires high precision process control. Referring now to FIG. 3, the capacitors in the periphery tends to distort due to the optical proximity effect during the photolithography procedure. As a result, the capacitance become smaller than the original design and the capacitance variation causes negative impacts on yield and performance of the DRAMs. In addition, those misshaped capacitors can further induce capacitance variation that causes reliability issue.
Analysis of the outmost mishaped capacitor problem reveals that it is a result of optical proximity effect during lithography process. In any photoresist exposing situation the local reaction speed up on the periphery area because the photoresist received more UV radiation. Because a level of uniform capacitance within the capacitor array must be met, this figure cannot be tolerated. In order to obtain uniform capacitor arrays, there is a need to provide a new set of layout criteria that pertains to capacitor array and their optimization within DRAM cells.
Accordingly, it is a primary object of the present invention to provide a method of designing a photomask for DRAM with the same area size of cylindrical capacitor arrays.
It is another object of the present invention to provide a method of forming a protection trench to protect cylindrical capacitor array during processing.
It is a further object of the present invention to provide a novel photomask layout to fabricate cylindrical capacitor arrays with uniform apacitance value.
These objects are accomplished by the method described below.
First, the capacitor array layout is automatically generated by an Electronic Design Automation (EDA) software. Next, the capacitor array patterns are copied to protection trench area with exact the same shape and pitch by using the EDA tool. Finally, the protection trench is finished by filling connecting patterns between gaps of the capacitor arrays, thus, forming a corrugated close loop protection trench after photoresist exposing and developing. This step is the key feature of the present invention. The key point of the present invention is that the shape of the protection trench is modified from rectangular strips to a mesh-like pattern that can effectively relieve the optical proximity effect of the prior art. Therefore, a level of uniform capacitance of the array can be met according to the embodiment of the present invention. A uniform area size of capacitor array can be accomplished according to the present invention.
In summary, with the present invention, a novel photomask layout to generate cylindrical capacitor arrays is provided for fabricating integrated circuit devices on the surface of a semiconductor substrate. In such a way, the mesh-like protection trench around capacitor arrays can also effectively protect the capacitor arrays from being damaged by solvent or acids during subsequent violent processes. Since the mesh-like trench makes the outmost capacitor arrays no longer stand in the periphery of the cell array, optical proximity effect can be avoided. Therefore, uniform capacitance can be obtained within the DRAM cell array, which eliminates the yield, performance, and reliability issues.